1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof and, more particularly, to a semiconductor device having a reduced leakage current. The semiconductor device includes a MOS transistor having a channel stopper below a field oxide film and a punch-through stopper in a region below and in the vicinity of the gate electrode of the MOS transistor.
2. Description of the Related Art
With the miniaturization of integrated circuit devices formed in a semiconductor substrate, there has been a need to miniaturize the constituent elements of the integrated circuit device and to increase the integration density thereof. In order to accommodate such requirements, the distance between elements, that is, the width of the field oxide film which is an element separating region, must also be minimized. Practically, a field oxide film having a width of 0.5 .mu.m or narrower is required. However, when the width of the element separating region is minimized, the element separating performance thereof is degraded. A punch-through phenomenon then occurs between adjacent elements which results in current leakage. In order to solve this problem, a method has been proposed in which a guard ring is provided in a portion of the semiconductor substrate which is immediately below the field oxide film. The guard ring is provided by forming an impurity region of the same conductivity type as that of the semiconductor substrate but having a partially increased impurity concentration. Another method is known in which an impurity region of the same conductivity type as that of the semiconductor substrate is formed not only in the portion of the semiconductor substrate which is immediately below the field oxide film but also in portions of the semiconductor substrate which are below the diffusion layer and the gate electrode. That is, the subject impurity region may be formed in the whole surface of the semiconductor substrate.
An example of a conventional MOS transistor utilizing this technique is shown in FIG. 4. This figure shows an example of a dynamic RAM cell constructed with a MOS transistor and a MOS capacitor, in which an element region is defined by forming a field oxide film 2 on a p type semiconductor substrate 1, a gate oxide film 4 and a gate electrode 5 are formed in the element region, and n type diffusion layers 6S and 6D are formed as respective source and drain, regions. A contact hole is formed in an inter-layer insulating film 8, and a storage electrode 9 is then formed which is connected to the drain region 6D through an n.sup.+ type diffusion layer 7. The MOS capacitor is formed by providing a capacitance insulating film 10 and then a plate electrode 11 on an upper surface of the storage electrode. Furthermore, a channel stopper 3A is formed immediately below the field oxide film 2 of the p type semiconductor substrate 1, and a punch-through stopper 3B contiguous to the channel stopper is formed immediately below the MOS transistor.
FIGS. 5(a) and 5(b) show cross sections of the dynamic RAM cell of FIG. 4, including the main fabrication steps thereof. First, as shown in FIG. 5(a), a field oxide film 2 which becomes the element separating region of the p type semiconductor substrate 1 is formed to a thickness of 400 nm by the LOCOS method, etc. In this technique, only the element separating region is exposed to thermal oxidation using a mask of an anti-oxidation material such as a silicon nitride film. The p.sup.+ type channel stopper 3A for preventing the punch-through phenomenon, that is, the structure for preventing current leakage between adjoining elements, is formed immediately below the element separating region. The p.sup.+ type channel stopper 3A may be formed by masking a region prior to forming the field oxide film 2 by thermal oxidation, and implanting boron ion into only those portions in which the field oxide film is to be formed. However, in order to reduce the number of fabrication steps, a method is used in which the channel stopper 3 is formed by implanting boron into the whole surface of the semiconductor substrate after the field oxide film 2 is formed. That is, boron is implanted by adjusting the implanting energy thereof such that, in the element separating region, boron penetrates the field oxide film 2 to form a region having a peak boron concentration value immediately below the field oxide film 2. In the element region, the implant extends slightly deeper into the semiconductor substrate as measured from the surface of the semiconductor substrate, and in the prior art example, the boron concentration has a peak value located about 400 nm below the substrate surface. According to this method, the high concentration p.sup.+ region functions as a channel stopper 3A in the region below the element separating region, and the high concentration p.sup.+ region functions as a punch-through stopper 3B of the transistor in the region below the gate of the transistor. That is, both of these effects can be obtained in a single operation.
Then, as shown in FIG. 5(b), after the gate oxide film 4 is formed in the element region defined by the field oxide film 2 to a thickness of 10-15 nm, an n.sup.+ type polysilicon film is deposited to a thickness of 200 nm and the gate electrode 5 (wordline) is patterned by etching the n.sup.+ type polysilicon film by a known photolithography technique. Then, the n type diffusion layers 6S and 6D are formed by implanting phosphorous ion at a dose of 3.times.10.sup.13 cm.sup.-2 using the gate electrode 5 and the field oxide film 2 as a mask. The junction depth of the n type diffusion layers 6S and 6D is about 0.3 .mu.m. These n type diffusion layers become the source and drain regions of the MOS transistor, respectively. Then, as the inter-layer insulating film 8, a silicon oxide film, for example, is deposited to a thickness of 500 nm. Thereafter, a contact hole 13 is formed using a photolithographic technique (not shown) to expose the n type diffusion layer 6D. Then, in order to reduce the contact resistance, phosphorous ion is again implanted (at a dose of about 1.times.10.sup.14 cm.sup.-2) into the contact portion, an n type polysilicon film is deposited on the whole surface of the substrate and, then, the polysilicon film is patterned to form the storage electrode 9 of the capacitor in the contact portion. Thereafter, the substrate is heat treated to thermally diffuse the impurity from the storage electrode 9 formed of the n type polysilicon through the contact hole into the n type diffusion layer 6D of the semiconductor substrate, and to thermally diffuse the impurity implanted into the contract portion of the storage electrode 9 into the n type diffusion layer 6D of the semiconductor substrate. This forms the extended n.sup.+ type diffusion layer 7. Alternatively, the storage electrode 9 may be made into an n type storage electrode by depositing a non-doped polysilicon film, patterning it and diffusing an impurity such as phosphorous therein. In such case, it is possible to form the n.sup.+ diffusion layer 7 simultaneously with the diffusion of phosphorous.
Thereafter, as shown in FIG. 4, capacitance insulating silicon oxide film 10 having a film thickness of 3-5 nm is formed on the upper and side surfaces of the storage electrode 9, and plate electrode 11 is formed from a 200 nm thick n type polysilicon film. The capacitance portion of the dynamic RAM cell is thus obtained. The final depth of the n.sup.+ diffusion layer 7 is about 0.4-0.5 .mu.m. The dynamic RAM cell is completed by forming a wiring (not shown) which becomes a bitline. That is, charge stored in the storage electrode 9 is transferred from the n.sup.+ type diffusion layer 7 to the n type diffusion layer 6S by ON/OFF operation of the gate electrode 5 of the MOS transistor, so that data can be input/output.
In the construction shown in FIG. 4, however, the n.sup.+ type diffusion layer 7 must be opened in the vicinity of the field oxide film 2 in order to miniaturize the element. Therefore, the n.sup.+ type diffusion layer 7 contacts the p.sup.+ type channel stopper 3A and the punch-through stopper 3B, resulting in a p.sup.+ -n.sup.+ junction 15. FIG. 6 shows a profile of the impurity concentration of the p.sup.+ -n.sup.+ junction 15, particularly, a profile thereof with respect to the punch-through stopper 3B. The profile of the p.sup.+ type punch-through stopper 3B has an impurity concentration peak at a depth of about 0.4 .mu.m and a concentration of about 5.times.10.sup.17 cm.sup.-3. On the other hand, the profile of the n.sup.+ type diffusion layer 7 has an impurity concentration peak at the surface of the substrate and a concentration of about 5.times.10.sup.18 cm.sup.-3. Therefore, the p.sup.+ -n.sup.+ junction 15 occurs at a depth of about 0.3 .mu.m. However, the p.sup.+ -n.sup.+ junction occurs at a depth where the p.sup.+ and n.sup.+ impurity concentrations of the p.sup.+ -n.sup.+ junction are not peaks.
As a result, when a potential is applied thereto, a depletion layer extends substantially on both the p.sup.+ and n.sup.+ sides. Particularly, when the depletion layer extends to the n.sup.+ side, there is a problem in that a G-R center (generation and recombination center which is related to the impurity concentration) in the n.sup.+ type diffusion layer 7 may enter the depletion layer such that the stored charge leaks to the substrate side through the G-R center as a leakage path. Furthermore, in order to prevent this phenomenon, the amount of impurity diffusion from the storage electrode 9 may be increased to a value that is sufficient to compensate for the density of the p.sup.+ type punch-through stopper 3B. However, there is a problem in that the n.sup.+ type diffusion layer 7 may expand substantially not only in the depth direction but also in the lateral direction. As a result, the interval against an adjacent n.sup.+ type diffusion layer may decrease, the breakdown voltage between n.sup.+ -n.sup.+ areas may be reduced and charge may leak.
Alternatively, in order to reduce the leakage current, the impurity concentration of the p.sup.+ type punch-through stopper 3B and the p.sup.+ type channel stopper 3A may be reduced to restrict the expansion of the depletion layer to the n.sup.+ type diffusion layer 7. However, the resulting performance of the stopper is insufficient and causes an increase in the leakage current. When a sufficient impurity concentration is set, the leakage at the p.sup.+ -n.sup.+ junction increases resulting in an increase in the leakage current, as described above. As a result, in the case of a dynamic RAM, the stored charge leaks, the charge holding characteristics thereof are substantially degraded and the reliability thereof is decreased.
Patent Application Laid-open No. S60-10769 gazette proposes a structure having a punch-through stopper 3B and a channel stopper 3A independently formed below a gate electrode 5 and a field oxide film 2, respectively, as shown in FIG. 7. In this structure there is no p.sup.+ type channel stopper below an n.sup.+ type diffusion layer 6D of a contact portion. Thus, it is possible to reduce the junction leakage from the bottom surface of the n.sup.+ type diffusion layer 6D. However, the side surface of the n.sup.+ type diffusion layer 6D is in contact with the channel stopper 3A below the field oxide film 2 as well as the p.sup.+ type punch-through stopper 3B below and in the vicinity of the gate electrode 5. Therefore, a p.sup.+ -n.sup.+ junction ultimately exists in a lateral surface portion of the n.sup.+ type diffusion layer 6D. Leakage from that junction is dominant and causes the same problem as described in the above prior art example.